1. Field of the Invention
The present invention relates to an entropy encoder/decoder based on EBCOT (embedded block coding with optimized truncation) or the like used in JPEG2000 for example.
This application claims the priority of the Japanese Patent Application No. 2002-045250 filed on Feb. 21, 2002, the entirety of which is incorporated by reference herein.
2. Description of the Related Art
Recently, there has been proposed a still picture compression method adopting a discrete wavelet transform called JPEG 2000 (ISO/IEC JTC 1/SC 29/WG1).
JPEG 2000 uses a coding called xe2x80x9cEBCOT (embedded block coding with optimized truncation)xe2x80x9d for the entropy coding in order to make the most of the features of the discrete wavelet transform.
EBCOT is implemented with the use of a bit modeling unit and an arithmetic encoder/decoder (the xe2x80x9cencoder/decoderxe2x80x9d will be referred to as xe2x80x9ccodecxe2x80x9d hereunder). The bit modeling unit provides a bit modeling in which an arithmetic-coding binary symbol and a context indicative of the arithmetic coding method are generated from the wavelet transform coefficient generated by the discrete wavelet transform, and effects the bit modeling reversely. The arithmetic codec fractionates a probability line correspondingly to an appearance probability of a generated sequence of symbols, makes an arithmetic coding to assign a binary decimal value indicative of a position in each of the fractions to a code corresponding to the code sequence, and effects the fractionation and arithmetic coding reversely.
Generally, FIFO (first-in first-out) memories are generally provided at input and output stages, respectively, of an EBCOT-based entropy codec circuit to continuously effect the coding and decoding without a break between them.
The EBCOT-based entropy codec having the FIFO memories provided at the input and output stages thereof is constructed as will be described in detail below with reference to FIGS. 1 and 2.
The entropy codec generally indicated with a reference 101 includes a wavelet transform coefficient input FIFO memory 102 to store supplied wavelet transform coefficients, code data input FIFO memory 103 to store supplied code data, code data output FIFO memory 104 to store to-be-outputted code data, wavelet transform coefficient output FIFO memory 105 to store to-be-outputted wavelet transform coefficients, bit modeling unit 106 and an arithmetic codec 107. It should be noted that the wavelet transform coefficient and code data to be supplied to or outputted from the entropy codec 101 are of 16 bits and 8 bits, respectively.
For coding, wavelet transform coefficients each of 16 bits are supplied from an external wavelet transform unit to the wavelet transform coefficient input FIFO memory 102 as shown in FIG. 1. The wavelet transform coefficient input FIFO memory 102 transfers wavelet transform coefficients stored therein one after another to the bit modeling unit 106. The bit modeling unit 106 generates a symbol and context from the wavelet transform coefficients thus received, and outputs them to the arithmetic codec 107. The arithmetic codec 107 generates a code data of 8 bits from the symbol and context thus received, and outputs the data to the code data output FIFO memory 104. The code data output FIFO memory 104 outputs 8-bit code data stored therein one after another to an external code forming device.
For decoding, an 8-bit code data is supplied from the external code forming device to the code data input FIFO memory 103, as shown in FIG. 2. The code data input FIFO memory 103 transfers code data stored therein one after another to the arithmetic codec 107. The arithmetic codec 107 generates a symbol from the code data thus received and a context supplied from the bit modeling unit 106, and outputs the symbol to the bit modeling unit 106. The bit modeling unit 106 generates a context and 16-bit wavelet transform coefficient from the symbol thus received. The bit modeling unit 106 outputs the context to the arithmetic codec 107 while outputting the 16-bit wavelet transform coefficient to the wavelet transform coefficient output FIFO memory 105. The wavelet transform coefficient output FIFO memory 105 outputs 16-bit wavelet coefficients stored therein one after another to the external wavelet transform unit.
Having the FIFO memories provided in the input and output stages, the entropy codec 101 can continuously effect the coding and decoding without a break between them.
In the EBCOT-based entropy coding/decoding, the data bit is different in length between before and after the coding and also between before and after the decoding. That is, the wavelet transform coefficient and code data after arithmetically coded are different in bit length from each other. Thus, the FIFO memories provided at the input and output stages of the EBCOT-based entropy codec should include a total of four FIFO memories for input of discrete wavelet coefficients, input of code data, output of discrete wavelet coefficients and for output of code data, respectively, as mentioned above.
Of such four FIFO memories, however, those intended for decoding are not in operation when in the coding mode of operation of the EBCOT-based entropy codec while those intended for coding are not in operation when in the decoding mode of operation. That is to say, the EBCOT-based entropy codec with the four FIFO memories has a redundant circuitry. Also, it is necessary to provide, outside the entropy codec 101, a selector to make a selection between input data and a selector to make a selection between output data. On this account, the data transfer rate of the entropy codec 101 will be lower because of the selection made by the selectors. Especially in case a memory used in common in the entire coding system (JPEG 2000 coding system, for example) is used as each FIFO memory, the data transfer rate will be considerably lower.
It is therefore an object of the present invention to overcome the above-mentioned drawbacks of the related art by providing an entropy encoder/decoder having a reduced circuitry scale and an improved data transfer rate.
The above object can be attained by providing an entropy encoder/decoder including, according to the present invention, an input FIFO (first-in first-out) memory to provisionally hold supplied data and output data held therein in their supplied order, an output FIFO memory to provisionally hold supplied data and output data held therein in their supplied order, a bit modeling means for making a bit modeling, an arithmetic coding/decoding means for making an arithmetic coding and effecting the arithmetic coding reversely, and a control means for controlling the number of data bits held in each of the input and output FIFO memories.
For the coding, the input FIFO memory is externally supplied with a multivalued data having a first number of bits and outputs the multivalued data to the bit modeling means, and for the decoding, it is externally supplied with a code data having a second number of bits, different from the first number of bits in the multivalued data and outputs the code data to the arithmetic coding/decoding means.
For the coding, the output FIFO memory is supplied with the code data having the second number of bits from the arithmetic coding/decoding means and outputs the code data to outside, and for the decoding, it is supplied with the multivalued data having the first number of bits from the bit modeling means and outputs the multivalued data to outside.
For the coding, the bit modeling means is supplied with the multivalued data from the input FIFO memory and generates an arithmetic-coding binary symbol and a context indicative of the arithmetic coding method from the multivalued data, and for the decoding, it is supplied with a symbol from the arithmetic coding/decoding means and generates a context and a multivalued data based on the symbol thus supplied.
For the coding, the arithmetic coding/decoding means is supplied with the symbol and context from the bit modeling means and generates a code data based on the symbol and context thus supplied, and for the decoding, it is supplied with the code data from the input FIFO memory and the context from the bit modeling means and generates a symbol based on the code data and context.
For the coding, the control means sets a valid number of bits held in the input FIFO memory as the above first number of bits and a valid number of bits held in the output FIFO memory as the above second number of bits, and for the decoding, it sets a valid number of bits held in the input FIFO memory as the above second number of bits and a valid number of bits held in the output FIFO memory as the above first number of bits.
These objects and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention when taken in conjunction with the accompanying drawings.